This invention relates to logic gate circuitry; and more particularly, it relates to those logic gate circuits that are made of nonsaturating bipolar transistors.
In the prior art, bipolar transistors are used to make both T.sup.2 L logic circuits and ECL logic circuits T.sup.2 L logic circuits consume less power the ECL logic circuits; however, T.sup.2 L logic circuits operate at a slower speed since their bipolar transistors are interconnected such that they saturate. By comparison, ECL logic circuits operate at a high speed; but they consume a large amount of power since their bipolar transistors are interconnected such that they do not saturate.
All of the circuitry of a conventional ECL logic gate is shown in FIG. 1. It receives two high or low input signal V.sub.i1 and V.sub.i2 ; then the left-hand portion of the gate forms a signal S.sub.1 of an intermediate voltage which represents the logical NOR of the input signals; and then the right-hand portion of the gate restores the voltage level of signal S.sub.1 to the high and low input signal levels. This gate has a switching speed of about 0.4 nanoseconds, a power dissipation of about 10 milliwatts, and it is commercially available in the MCA II gate array series from Motorola.
One problem, however, with the FIG. 1 ECL logic gate is that it includes a large number of components. Specifically, it includes five transistors T1, T2, T3, T4, and T5; four resistors R1, R2, R3, and R4; and four voltage buses B1, B2, B3, and B4. Each of these components occupies a certain amount of space on a semiconductor chip; and thus they limit the number of gates that can be integrated into the chip.
Another problem with the FIG. 1 ECL logic gate is that it consumes too much power. That power which is dissipated in the left-hand portion of the FIG. 1 gate can be expressed as V.sub.EE I.sub.O, and that power which is dissipated in the right-hand portion of the FIG. 1 gate can be expressed as (1/2)(I.sub.0 +0.81.sub.0)V.sub.EE.
Current I.sub.0 in the left-hand term is a constant current which always flows through either transistor T1, T2, or T3; and it is generated by the current source which is formed by the combination of transistor T4 and resistor R3. In the right-hand term, the current 1/2(I.sub.0 +0.81.sub.0) is the average current which flows through transistor T5. Current I.sub.0 flows when the output signal V.sub.0 is high, and current 0.8 I.sub.0 flows when the output V.sub.0 signal is low.
Accordingly, in an effort to overcome the above problem, a primary object of the invention is to provide an improved nonsaturating bipolar logic gate which operates at essentially the same speed as an ECL logic gate but which requires substantially fewer components and dissipates substantially less power.